The invention relates to a sync circuit arrangement for producing a synchronizing pulse upon detection of a frame codeword containing a multiplicity of repeated first words and at least one second word.
Such a circuit arrangement is known from EP-A2 0 103 163. Such an arrangement is necessary, for example, when a frame-structured binary signal is to be partitioned into sub-signals by means of a demultiplexer. Especially the partitioning of a synchronous transport modules STM-16 into four synchronous transport modules STM-4 (cf. in this respect the CCITT Recommendations G 707, G 708, G 709) is considered here and in the following embodiments. The frame codeword of a synchronous transport module STM-16 is 768 bits long and consists of 48 repetitions of a word A1 having the bit sequence 11110110, as well as subsequent forty-eight repetitions of a second word A2 having the bit sequence 00101000.
Producing a synchronizing (sync) pulse from such a frame codeword with the prior-art circuit arrangement would imply considerable circuitry and cost. For example, the first memory matrix used for storing the incoming bit stream so that it can be compared with the known codeword should then comprise 771 memory locations that can be queried.